A VHDL-AMS Simulation Environment for an UWB Impulse Radio Transceiver

Ultra-Wide-Band (UWB) communication based on the impulse radio paradigm is becoming increasingly popular. According to the IEEE 802.15 WPAN Low Rate Alternative PHY Task Group 4a, UWB will play a major role in localization applications, due to the high time resolution of UWB signals which allow accurate indirect measurements of distance between transceivers. Key for the successful implementation of UWB transceivers is the level of integration that will be reached, for which a simulation environment that helps take appropriate design decisions is crucial. Owing to this motivation, in this paper we propose a multiresolution UWB simulation environment based on the VHDL-AMS hardware description language, along with a proper methodology which helps tackle the complexity of designing a mixed-signal UWB System-on-Chip. We applied the methodology and used the simulation environment for the specification and design of an UWB transceiver based on the energy detection principle. As a by-product, simulation results show the effectiveness of UWB in the so-called ranging application, that is the accurate evaluation of the distance between a couple of transceivers using the two-way-ranging metho

A Mixed-Signal Demodulator for a Low-Complexity IR-UWB Receiver: Methodology, Simulation and Design

This works presents an integrated 0.18μm CMOS 2-PPM demodulator based on a switched capacitor network for an Energy Detection Impulse-Radio UWB receiver. The circuit has been designed using a top-down methodology that allows to discover the impact of low-level non-idealities on system-level performance. Through the use of a mixed signal simulation environment, performance figures have been obtained which helped evaluate the influence at system-level of the non-idealities of the most critical block. Results show that the circuit allows the replacement of the ADC typically employed in Energy Detection receivers and provides about infinite equivalent quantization resolution. The demodulator achieves 190 pJ/bit at 1.8V

Hardware Acceleration of Beamforming in a UWB Imaging Unit for Breast Cancer Detection

The Ultrawideband (UWB) imaging technique for breast cancer detection is based on the fact that cancerous cells have different dielectric characteristics than healthy tissues.When a UWB pulse in the microwave range strikes a cancerous region, the reflected signal is more intense than the backscatter originating from the surrounding fat tissue. A UWB imaging system consists of transmitters, receivers, and antennas for the RF part, and of a digital back-end for processing the received signals. In this paper we focus on the imaging unit, which elaborates the acquired data and produces 2D or 3D maps of reflected energies.We show that one of the processing tasks, Beamforming, is the most timing critical and cannot be executed in software by a standard microprocessor in a reasonable time.We thus propose a specialized hardware accelerator for it.We design the accelerator in VHDL and test it in an FPGA-based prototype. We also evaluate its performance when implemented on a CMOS 45nm ASIC technology. The speed-up with respect to a software implementation is on the order of tens to hundreds, depending on the degree of parallelism permitted by the target technology

Effects of Temperature in Deep-Submicron Global Interconnect Optimization in Future Technology Nodes

The resistance of on-chip interconnects and the current drive of transistors are strongly temperature-dependent. As a result, the interconnect performance in Deep-Submicron technologies is affected by temperature in a substantial proportion. In this paper we evaluate thermal effects in global RLC interconnects and quantify their impact in a standard optimization procedure based on repeaters insertion. By evaluating the difference between a simple RC and an accurate RLC model, we show how the temperature induced increase of resistance may reduce the impact of inductance. We also project the evolution of such effects in future CMOS technologies, according to the semiconductor roadmap

MEDEA: A Hybrid Shared-memory/Message-passing Multiprocessor NoC-based Architecture

The shared-memory model has been adopted, both for data exchange as well as synchronization using semaphores in almost every on-chip multiprocessor implementation, ranging from general purpose chip multiprocessors (CMPs) to domain specific multi-core graphics processing units (GPUs). Low-latency synchronization is desirable but is hard to achieve in practice due to the memory hierarchy. On the contrary, an explicit exchange of synchronization tokens among the processing elements through dedicated on-chip links would be beneficial for the overall system performance. In this paper we propose the Medea NoC-based framework, a hybrid shared-memory/message-passing approach. Medea has been modeled with a fast, cycle-accurate SystemC implementation enabling a fast system exploration varying several parameters like number and types of cores, cache size and policy and NoC features. In addition, every SystemC block has its RTL counterpart for physical implementation on FPGAs and ASICs. A parallel version of the Jacobi algorithm has been used as a test application to validate the metodology. Results confirm expectations about performance and effectiveness of system exploration and design

Power-Gating Technique for Network-on-Chip Buffers

A new approach to reducing leakage power in network-on-chip buffers is presented. The non-uniformity of buffer utilisation is leveraged across the network and power-gating is applied to scarcely utilised buffers. Instead of turning-off the buffers completely, a buffer portion is kept turned-on. This design choice has a significant performance benefit because the buffer is always able to receive network packets. Design aspects and trade-offs in a 45 nm CMOS technology are discussed and results obtained over video application benchmarks are presented. It is shown that it is possible to reduce buffer leakage by 40% without performance penalt

Digital Circuits in a Multi-Functional SAGFET MMIC Technology

In this paper a possible implementation of digital circuits in a MMIC SAGFET/SAGHEMT technology is described. This technology has been developed at the Alenia Marconi Systems (AMS) and it is well suited for the integration of digital and microwave parts in the same GaAs substrate. A test circuit with FET’s for DC/AC characterization, inverter chains, ring oscillators and frequency dividers has been designed and is now under fabrication at AMS. Since now only Depletion MESFET transistors were available. However, the technology is still growing and in the near future Enhancement and Depletion MESFET and HEMT transistors will allow the implementation of E/D logic circuits